The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
References
Configurations
History
21 Nov 2024, 05:43
Type | Values Removed | Values Added |
---|---|---|
References | () https://riscv.org/news/2021/08/video-glitching-risc-v-chips-mtvec-corruption-for-hardening-isa-adam-zabrocki-and-alex-matrosov-def-con-29/ - Exploit, Vendor Advisory |
23 Aug 2021, 20:30
Type | Values Removed | Values Added |
---|---|---|
CPE | cpe:2.3:a:risc-v:instruction_set_manual:*:*:*:*:*:*:*:* | |
CVSS |
v2 : v3 : |
v2 : 7.5
v3 : 9.8 |
CWE | CWE-908 | |
References | (CONFIRM) https://riscv.org/news/2021/08/video-glitching-risc-v-chips-mtvec-corruption-for-hardening-isa-adam-zabrocki-and-alex-matrosov-def-con-29/ - Exploit, Vendor Advisory |
13 Aug 2021, 16:24
Type | Values Removed | Values Added |
---|---|---|
New CVE |
Information
Published : 2021-08-13 16:15
Updated : 2024-11-21 05:43
NVD link : CVE-2021-1104
Mitre link : CVE-2021-1104
CVE.ORG link : CVE-2021-1104
JSON object : View
Products Affected
risc-v
- instruction_set_manual
CWE
CWE-908
Use of Uninitialized Resource