CVE-2025-56301

  1. OpenCVE
  2. Vulnerabilities (CVE)
  3. CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.

7.5 /10

CVSS v3 : HIGH

V3 Legend

Vector :

Exploitability : 3.9 / Impact : 3.6

Attack Vector NETWORK

Attack Complexity LOW

Privileges Required NONE

User Interaction NONE

Confidentiality Impact NONE

Integrity Impact NONE

Availability Impact HIGH

Scope UNCHANGED

References
Link Resource
https://github.com/chipsalliance/rocket-chip Product
https://github.com/chipsalliance/rocket-chip/blob/f517abbf41abb65cea37421d3559f9739efd00a9/src/main/scala/rocket/CSR.scala Product
https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala Product
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-56301/details.md Exploit Third Party Advisory
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications Product
Configurations

Configuration 1 (hide)

cpe:2.3:a:chipsalliance:rocket-chip:2025-01-29:*:*:*:*:*:*:*
History

17 Oct 2025, 20:45

Type Values Removed Values Added
First Time Chipsalliance
Chipsalliance rocket-chip
CPE cpe:2.3:a:chipsalliance:rocket-chip:2025-01-29:*:*:*:*:*:*:*
References () https://github.com/chipsalliance/rocket-chip - () https://github.com/chipsalliance/rocket-chip - Product
References () https://github.com/chipsalliance/rocket-chip/blob/f517abbf41abb65cea37421d3559f9739efd00a9/src/main/scala/rocket/CSR.scala - () https://github.com/chipsalliance/rocket-chip/blob/f517abbf41abb65cea37421d3559f9739efd00a9/src/main/scala/rocket/CSR.scala - Product
References () https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala - () https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/CSR.scala - Product
References () https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-56301/details.md - () https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-56301/details.md - Exploit, Third Party Advisory
References () https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications - () https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications - Product

01 Oct 2025, 20:18

Type Values Removed Values Added
CWE CWE-1281
CVSS v2 : unknown
v3 : unknown 		v2 : unknown
v3 : 7.5

30 Sep 2025, 15:15

Type Values Removed Values Added
New CVE
Information

Published : 2025-09-30 15:15

Updated : 2025-10-17 20:45

NVD link : CVE-2025-56301

Mitre link : CVE-2025-56301

CVE.ORG link : CVE-2025-56301

JSON object : View

Products Affected

chipsalliance

  • rocket-chip
CWE
CWE-1281

Sequence of Processor Instructions Leads to Unexpected Behavior (Halt and Catch Fire)